; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\output\main.o --depend=.\output\main.d --device=DARMSTM --apcs=interwork -O3 -I.\ -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB --omf_browse=.\output\main.crf main.c]
                          THUMB

                          AREA ||i.CheckBackupReg||, CODE, READONLY, ALIGN=2

                  CheckBackupReg PROC
;;;366    *******************************************************************************/
;;;367    u8 CheckBackupReg(u16 FirstBackupData)
000000  b510              PUSH     {r4,lr}
;;;368    {
000002  4604              MOV      r4,r0
;;;369      if(BKP_ReadBackupRegister(BKP_DR1) != FirstBackupData) return 1;
000004  2004              MOVS     r0,#4
000006  f7fffffe          BL       BKP_ReadBackupRegister
00000a  42a0              CMP      r0,r4
00000c  d001              BEQ      |L1.18|
00000e  2001              MOVS     r0,#1
;;;370      if(BKP_ReadBackupRegister(BKP_DR2) != (BKP->DR1 + 0x5A)) return 2;
;;;371      if(BKP_ReadBackupRegister(BKP_DR3) != (BKP->DR2 + 0x3C)) return 3;
;;;372      if(BKP_ReadBackupRegister(BKP_DR4) != (BKP->DR3 + 0xA5)) return 4;
;;;373      if(BKP_ReadBackupRegister(BKP_DR5) != (BKP->DR4 + 0x06)) return 5;
;;;374      if(BKP_ReadBackupRegister(BKP_DR6) != (BKP->DR5 + 0x78)) return 6;
;;;375      if(BKP_ReadBackupRegister(BKP_DR7) != (BKP->DR6 + 0xFF)) return 7;
;;;376      if(BKP_ReadBackupRegister(BKP_DR8) != (BKP->DR7 + 0xB4)) return 8;
;;;377      if(BKP_ReadBackupRegister(BKP_DR9) != (BKP->DR8 + 0x1E)) return 9;
;;;378      if(BKP_ReadBackupRegister(BKP_DR10) != (BKP->DR9 + 0xD4)) return 10;
;;;379    
;;;380      return 0;
;;;381    }
000010  bd10              POP      {r4,pc}
                  |L1.18|
000012  2008              MOVS     r0,#8                 ;370
000014  f7fffffe          BL       BKP_ReadBackupRegister
000018  4c2c              LDR      r4,|L1.204|
00001a  f8b41c04          LDRH     r1,[r4,#0xc04]        ;370
00001e  315a              ADDS     r1,r1,#0x5a           ;370
000020  4288              CMP      r0,r1                 ;370
000022  d001              BEQ      |L1.40|
000024  2002              MOVS     r0,#2                 ;370
000026  bd10              POP      {r4,pc}
                  |L1.40|
000028  200c              MOVS     r0,#0xc               ;371
00002a  f7fffffe          BL       BKP_ReadBackupRegister
00002e  f8b41c08          LDRH     r1,[r4,#0xc08]        ;371
000032  313c              ADDS     r1,r1,#0x3c           ;371
000034  4288              CMP      r0,r1                 ;371
000036  d001              BEQ      |L1.60|
000038  2003              MOVS     r0,#3                 ;371
00003a  bd10              POP      {r4,pc}
                  |L1.60|
00003c  2010              MOVS     r0,#0x10              ;372
00003e  f7fffffe          BL       BKP_ReadBackupRegister
000042  f8b41c0c          LDRH     r1,[r4,#0xc0c]        ;372
000046  31a5              ADDS     r1,r1,#0xa5           ;372
000048  4288              CMP      r0,r1                 ;372
00004a  d001              BEQ      |L1.80|
00004c  2004              MOVS     r0,#4                 ;372
00004e  bd10              POP      {r4,pc}
                  |L1.80|
000050  2014              MOVS     r0,#0x14              ;373
000052  f7fffffe          BL       BKP_ReadBackupRegister
000056  f8b41c10          LDRH     r1,[r4,#0xc10]        ;373
00005a  1d89              ADDS     r1,r1,#6              ;373
00005c  4288              CMP      r0,r1                 ;373
00005e  d001              BEQ      |L1.100|
000060  2005              MOVS     r0,#5                 ;373
000062  bd10              POP      {r4,pc}
                  |L1.100|
000064  2018              MOVS     r0,#0x18              ;374
000066  f7fffffe          BL       BKP_ReadBackupRegister
00006a  f8b41c14          LDRH     r1,[r4,#0xc14]        ;374
00006e  3178              ADDS     r1,r1,#0x78           ;374
000070  4288              CMP      r0,r1                 ;374
000072  d001              BEQ      |L1.120|
000074  2006              MOVS     r0,#6                 ;374
000076  bd10              POP      {r4,pc}
                  |L1.120|
000078  201c              MOVS     r0,#0x1c              ;375
00007a  f7fffffe          BL       BKP_ReadBackupRegister
00007e  f8b41c18          LDRH     r1,[r4,#0xc18]        ;375
000082  31ff              ADDS     r1,r1,#0xff           ;375
000084  4288              CMP      r0,r1                 ;375
000086  d001              BEQ      |L1.140|
000088  2007              MOVS     r0,#7                 ;375
00008a  bd10              POP      {r4,pc}
                  |L1.140|
00008c  2020              MOVS     r0,#0x20              ;376
00008e  f7fffffe          BL       BKP_ReadBackupRegister
000092  f8b41c1c          LDRH     r1,[r4,#0xc1c]        ;376
000096  31b4              ADDS     r1,r1,#0xb4           ;376
000098  4288              CMP      r0,r1                 ;376
00009a  d001              BEQ      |L1.160|
00009c  2008              MOVS     r0,#8                 ;376
00009e  bd10              POP      {r4,pc}
                  |L1.160|
0000a0  2024              MOVS     r0,#0x24              ;377
0000a2  f7fffffe          BL       BKP_ReadBackupRegister
0000a6  f8b41c20          LDRH     r1,[r4,#0xc20]        ;377
0000aa  311e              ADDS     r1,r1,#0x1e           ;377
0000ac  4288              CMP      r0,r1                 ;377
0000ae  d001              BEQ      |L1.180|
0000b0  2009              MOVS     r0,#9                 ;377
0000b2  bd10              POP      {r4,pc}
                  |L1.180|
0000b4  2028              MOVS     r0,#0x28              ;378
0000b6  f7fffffe          BL       BKP_ReadBackupRegister
0000ba  f8b41c24          LDRH     r1,[r4,#0xc24]        ;378
0000be  31d4              ADDS     r1,r1,#0xd4           ;378
0000c0  4288              CMP      r0,r1                 ;378
0000c2  d001              BEQ      |L1.200|
0000c4  200a              MOVS     r0,#0xa               ;378
0000c6  bd10              POP      {r4,pc}
                  |L1.200|
0000c8  2000              MOVS     r0,#0                 ;380
0000ca  bd10              POP      {r4,pc}
;;;382    
                          ENDP

                  |L1.204|
                          DCD      0x40006000

                          AREA ||i.GPIO_Configuration||, CODE, READONLY, ALIGN=2

                  GPIO_Configuration PROC
;;;190    *******************************************************************************/
;;;191    void GPIO_Configuration(void)
000000  b538              PUSH     {r3-r5,lr}
;;;192    {
;;;193      GPIO_InitTypeDef GPIO_InitStructure;
;;;194    
;;;195    
;;;196      /* Configure USART1 Tx (PA.09) as alternate function push-pull */
;;;197      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
000002  f44f7000          MOV      r0,#0x200
000006  f8ad0000          STRH     r0,[sp,#0]
;;;198      GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00000a  2018              MOVS     r0,#0x18
00000c  f88d0003          STRB     r0,[sp,#3]
;;;199      GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
;;;200      GPIO_Init(GPIOA, &GPIO_InitStructure);
000010  4d0f              LDR      r5,|L2.80|
000012  2403              MOVS     r4,#3                 ;199
000014  f88d4002          STRB     r4,[sp,#2]            ;199
000018  4669              MOV      r1,sp
00001a  4628              MOV      r0,r5
00001c  f7fffffe          BL       GPIO_Init
;;;201        
;;;202      /* Configure USART1 Rx (PA.10) as input floating */
;;;203      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
000020  1528              ASRS     r0,r5,#20
000022  f8ad0000          STRH     r0,[sp,#0]
;;;204      GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
000026  2004              MOVS     r0,#4
000028  f88d0003          STRB     r0,[sp,#3]
;;;205      GPIO_Init(GPIOA, &GPIO_InitStructure);
00002c  4669              MOV      r1,sp
00002e  4628              MOV      r0,r5
000030  f7fffffe          BL       GPIO_Init
;;;206    
;;;207    
;;;208      /* Configure PC.06, PC.07, PC.08 and PC.09 as Output push-pull */
;;;209      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_6 | GPIO_Pin_7;
000034  f44f7070          MOV      r0,#0x3c0
000038  f8ad0000          STRH     r0,[sp,#0]
;;;210      GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00003c  f88d4002          STRB     r4,[sp,#2]
;;;211      GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
000040  2010              MOVS     r0,#0x10
000042  f88d0003          STRB     r0,[sp,#3]
;;;212      GPIO_Init(GPIOC, &GPIO_InitStructure);
000046  4669              MOV      r1,sp
000048  4802              LDR      r0,|L2.84|
00004a  f7fffffe          BL       GPIO_Init
;;;213    }
00004e  bd38              POP      {r3-r5,pc}
;;;214    
                          ENDP

                  |L2.80|
                          DCD      0x40010800
                  |L2.84|
                          DCD      0x40011000

                          AREA ||i.IsBackupRegReset||, CODE, READONLY, ALIGN=1

                  IsBackupRegReset PROC
;;;391    *******************************************************************************/
;;;392    u8 IsBackupRegReset(void)
000000  b510              PUSH     {r4,lr}
;;;393    {
;;;394      if(BKP_ReadBackupRegister(BKP_DR1) != 0x0000) return 1;
000002  2004              MOVS     r0,#4
000004  f7fffffe          BL       BKP_ReadBackupRegister
000008  b108              CBZ      r0,|L3.14|
00000a  2001              MOVS     r0,#1
;;;395      if(BKP_ReadBackupRegister(BKP_DR2) != 0x0000) return 2;
;;;396      if(BKP_ReadBackupRegister(BKP_DR3) != 0x0000) return 3;
;;;397      if(BKP_ReadBackupRegister(BKP_DR4) != 0x0000) return 4;
;;;398      if(BKP_ReadBackupRegister(BKP_DR5) != 0x0000) return 5;
;;;399      if(BKP_ReadBackupRegister(BKP_DR6) != 0x0000) return 6;
;;;400      if(BKP_ReadBackupRegister(BKP_DR7) != 0x0000) return 7;
;;;401      if(BKP_ReadBackupRegister(BKP_DR8) != 0x0000) return 8;
;;;402      if(BKP_ReadBackupRegister(BKP_DR9) != 0x0000) return 9;
;;;403      if(BKP_ReadBackupRegister(BKP_DR10) != 0x0000) return 10;
;;;404    
;;;405      return 0;
;;;406    }
00000c  bd10              POP      {r4,pc}
                  |L3.14|
00000e  2008              MOVS     r0,#8                 ;395
000010  f7fffffe          BL       BKP_ReadBackupRegister
000014  b108              CBZ      r0,|L3.26|
000016  2002              MOVS     r0,#2                 ;395
000018  bd10              POP      {r4,pc}
                  |L3.26|
00001a  200c              MOVS     r0,#0xc               ;396
00001c  f7fffffe          BL       BKP_ReadBackupRegister
000020  b108              CBZ      r0,|L3.38|
000022  2003              MOVS     r0,#3                 ;396
000024  bd10              POP      {r4,pc}
                  |L3.38|
000026  2010              MOVS     r0,#0x10              ;397
000028  f7fffffe          BL       BKP_ReadBackupRegister
00002c  b108              CBZ      r0,|L3.50|
00002e  2004              MOVS     r0,#4                 ;397
000030  bd10              POP      {r4,pc}
                  |L3.50|
000032  2014              MOVS     r0,#0x14              ;398
000034  f7fffffe          BL       BKP_ReadBackupRegister
000038  b108              CBZ      r0,|L3.62|
00003a  2005              MOVS     r0,#5                 ;398
00003c  bd10              POP      {r4,pc}
                  |L3.62|
00003e  2018              MOVS     r0,#0x18              ;399
000040  f7fffffe          BL       BKP_ReadBackupRegister
000044  b108              CBZ      r0,|L3.74|
000046  2006              MOVS     r0,#6                 ;399
000048  bd10              POP      {r4,pc}
                  |L3.74|
00004a  201c              MOVS     r0,#0x1c              ;400
00004c  f7fffffe          BL       BKP_ReadBackupRegister
000050  b108              CBZ      r0,|L3.86|
000052  2007              MOVS     r0,#7                 ;400
000054  bd10              POP      {r4,pc}
                  |L3.86|
000056  2020              MOVS     r0,#0x20              ;401
000058  f7fffffe          BL       BKP_ReadBackupRegister
00005c  b108              CBZ      r0,|L3.98|
00005e  2008              MOVS     r0,#8                 ;401
000060  bd10              POP      {r4,pc}
                  |L3.98|
000062  2024              MOVS     r0,#0x24              ;402
000064  f7fffffe          BL       BKP_ReadBackupRegister
000068  b108              CBZ      r0,|L3.110|
00006a  2009              MOVS     r0,#9                 ;402
                  |L3.108|
00006c  bd10              POP      {r4,pc}
                  |L3.110|
00006e  2028              MOVS     r0,#0x28              ;403
000070  f7fffffe          BL       BKP_ReadBackupRegister
000074  2800              CMP      r0,#0                 ;403
000076  d0f9              BEQ      |L3.108|
000078  200a              MOVS     r0,#0xa               ;403
00007a  bd10              POP      {r4,pc}
;;;407    
                          ENDP


                          AREA ||i.NVIC_Configuration||, CODE, READONLY, ALIGN=1

                  NVIC_Configuration PROC
;;;221    *******************************************************************************/
;;;222    void NVIC_Configuration(void)
000000  b508              PUSH     {r3,lr}
;;;223    {
;;;224      NVIC_InitTypeDef NVIC_InitStructure;
;;;225    
;;;226    #ifdef  VECT_TAB_RAM  
;;;227      /* Set the Vector Table base location at 0x20000000 */ 
;;;228      NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); 
;;;229    #else  /* VECT_TAB_FLASH  */
;;;230      /* Set the Vector Table base location at 0x08000000 */ 
;;;231      NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);   
000002  2100              MOVS     r1,#0
000004  f04f6000          MOV      r0,#0x8000000
000008  f7fffffe          BL       NVIC_SetVectorTable
;;;232    #endif
;;;233    
;;;234      /* Enable TAMPER IRQChannel */
;;;235      NVIC_InitStructure.NVIC_IRQChannel = TAMPER_IRQChannel;
00000c  2002              MOVS     r0,#2
00000e  f88d0000          STRB     r0,[sp,#0]
;;;236      NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
000012  2000              MOVS     r0,#0
000014  f88d0001          STRB     r0,[sp,#1]
;;;237      NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
000018  f88d0002          STRB     r0,[sp,#2]
;;;238      NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00001c  2001              MOVS     r0,#1
00001e  f88d0003          STRB     r0,[sp,#3]
;;;239      NVIC_Init(&NVIC_InitStructure);
000022  4668              MOV      r0,sp
000024  f7fffffe          BL       NVIC_Init
;;;240    }
000028  bd08              POP      {r3,pc}
;;;241    
                          ENDP


                          AREA ||i.PrintBackupReg||, CODE, READONLY, ALIGN=2

                  PrintBackupReg PROC
;;;416    *******************************************************************************/
;;;417    void PrintBackupReg(void)
000000  b510              PUSH     {r4,lr}
;;;418    {
;;;419      //u16 e;
;;;420      //e = BKP_DR1;
;;;421      //printf("e  = 0x%x\t",e);
;;;422      printf("\nNow the data in DRx are:\n");
000002  a025              ADR      r0,|L5.152|
000004  f7fffffe          BL       __2printf
;;;423      printf("DR1  = 0x%04X\t",BKP_ReadBackupRegister(BKP_DR1)); 
000008  2004              MOVS     r0,#4
00000a  f7fffffe          BL       BKP_ReadBackupRegister
00000e  4601              MOV      r1,r0
000010  a028              ADR      r0,|L5.180|
000012  f7fffffe          BL       __2printf
;;;424      printf("DR2  = 0x%04X\t",BKP_ReadBackupRegister(BKP_DR2));
000016  2008              MOVS     r0,#8
000018  f7fffffe          BL       BKP_ReadBackupRegister
00001c  4601              MOV      r1,r0
00001e  a029              ADR      r0,|L5.196|
000020  f7fffffe          BL       __2printf
;;;425      printf("DR3  = 0x%04X\t",BKP_ReadBackupRegister(BKP_DR3));
000024  200c              MOVS     r0,#0xc
000026  f7fffffe          BL       BKP_ReadBackupRegister
00002a  4601              MOV      r1,r0
00002c  a029              ADR      r0,|L5.212|
00002e  f7fffffe          BL       __2printf
;;;426      printf("DR4  = 0x%04X\t",BKP_ReadBackupRegister(BKP_DR4));
000032  2010              MOVS     r0,#0x10
000034  f7fffffe          BL       BKP_ReadBackupRegister
000038  4601              MOV      r1,r0
00003a  a02a              ADR      r0,|L5.228|
00003c  f7fffffe          BL       __2printf
;;;427      printf("DR5  = 0x%04X\t\n",BKP_ReadBackupRegister(BKP_DR5));
000040  2014              MOVS     r0,#0x14
000042  f7fffffe          BL       BKP_ReadBackupRegister
000046  4601              MOV      r1,r0
000048  a02a              ADR      r0,|L5.244|
00004a  f7fffffe          BL       __2printf
;;;428      printf("DR6  = 0x%04X\t",BKP_ReadBackupRegister(BKP_DR6));
00004e  2018              MOVS     r0,#0x18
000050  f7fffffe          BL       BKP_ReadBackupRegister
000054  4601              MOV      r1,r0
000056  a02b              ADR      r0,|L5.260|
000058  f7fffffe          BL       __2printf
;;;429      printf("DR7  = 0x%04X\t",BKP_ReadBackupRegister(BKP_DR7));
00005c  201c              MOVS     r0,#0x1c
00005e  f7fffffe          BL       BKP_ReadBackupRegister
000062  4601              MOV      r1,r0
000064  a02b              ADR      r0,|L5.276|
000066  f7fffffe          BL       __2printf
;;;430      printf("DR8  = 0x%04X\t",BKP_ReadBackupRegister(BKP_DR8));
00006a  2020              MOVS     r0,#0x20
00006c  f7fffffe          BL       BKP_ReadBackupRegister
000070  4601              MOV      r1,r0
000072  a02c              ADR      r0,|L5.292|
000074  f7fffffe          BL       __2printf
;;;431      printf("DR9  = 0x%04X\t",BKP_ReadBackupRegister(BKP_DR9));
000078  2024              MOVS     r0,#0x24
00007a  f7fffffe          BL       BKP_ReadBackupRegister
00007e  4601              MOV      r1,r0
000080  a02c              ADR      r0,|L5.308|
000082  f7fffffe          BL       __2printf
;;;432      printf("DR10 = 0x%04X\t\n",BKP_ReadBackupRegister(BKP_DR10));
000086  2028              MOVS     r0,#0x28
000088  f7fffffe          BL       BKP_ReadBackupRegister
00008c  4601              MOV      r1,r0
00008e  e8bd4010          POP      {r4,lr}
000092  a02c              ADR      r0,|L5.324|
000094  f7ffbffe          B.W      __2printf
;;;433    }
;;;434    
                          ENDP

                  |L5.152|
000098  0a4e6f7720746865206461746120696e20445278206172653a0a00        DCB      "\nNow the data in DRx are:\n",0
0000b3  00                DCB      0
                  |L5.180|
0000b4  44523120203d203078253034580900        DCB      "DR1  = 0x%04X\t",0
0000c3  00                DCB      0
                  |L5.196|
0000c4  44523220203d203078253034580900        DCB      "DR2  = 0x%04X\t",0
0000d3  00                DCB      0
                  |L5.212|
0000d4  44523320203d203078253034580900        DCB      "DR3  = 0x%04X\t",0
0000e3  00                DCB      0
                  |L5.228|
0000e4  44523420203d203078253034580900        DCB      "DR4  = 0x%04X\t",0
0000f3  00                DCB      0
                  |L5.244|
0000f4  44523520203d20307825303458090a00        DCB      "DR5  = 0x%04X\t\n",0
                  |L5.260|
000104  44523620203d203078253034580900        DCB      "DR6  = 0x%04X\t",0
000113  00                DCB      0
                  |L5.276|
000114  44523720203d203078253034580900        DCB      "DR7  = 0x%04X\t",0
000123  00                DCB      0
                  |L5.292|
000124  44523820203d203078253034580900        DCB      "DR8  = 0x%04X\t",0
000133  00                DCB      0
                  |L5.308|
000134  44523920203d203078253034580900        DCB      "DR9  = 0x%04X\t",0
000143  00                DCB      0
                  |L5.324|
000144  44523130203d20307825303458090a00        DCB      "DR10 = 0x%04X\t\n",0

                          AREA ||i.RCC_Configuration||, CODE, READONLY, ALIGN=2

                  RCC_Configuration PROC
;;;130    *******************************************************************************/
;;;131    void RCC_Configuration(void)
000000  b510              PUSH     {r4,lr}
;;;132    {
;;;133      /* RCC system reset(for debug purpose) */
;;;134      RCC_DeInit();
000002  f7fffffe          BL       RCC_DeInit
;;;135    
;;;136      /* Enable HSE */
;;;137      RCC_HSEConfig(RCC_HSE_ON);
000006  f44f3480          MOV      r4,#0x10000
00000a  4620              MOV      r0,r4
00000c  f7fffffe          BL       RCC_HSEConfig
;;;138    
;;;139      /* Wait till HSE is ready */
;;;140      HSEStartUpStatus = RCC_WaitForHSEStartUp();
000010  f7fffffe          BL       RCC_WaitForHSEStartUp
000014  4917              LDR      r1,|L6.116|
000016  7008              STRB     r0,[r1,#0]
;;;141    
;;;142      if(HSEStartUpStatus == SUCCESS)
000018  b2c0              UXTB     r0,r0
00001a  2801              CMP      r0,#1
00001c  d122              BNE      |L6.100|
;;;143      {
;;;144        /* HCLK = SYSCLK */
;;;145        RCC_HCLKConfig(RCC_SYSCLK_Div1); 
00001e  2000              MOVS     r0,#0
000020  f7fffffe          BL       RCC_HCLKConfig
;;;146      
;;;147        /* PCLK2 = HCLK */
;;;148        RCC_PCLK2Config(RCC_HCLK_Div1); 
000024  2000              MOVS     r0,#0
000026  f7fffffe          BL       RCC_PCLK2Config
;;;149    
;;;150        /* PCLK1 = HCLK/2 */
;;;151        RCC_PCLK1Config(RCC_HCLK_Div2);
00002a  11a0              ASRS     r0,r4,#6
00002c  f7fffffe          BL       RCC_PCLK1Config
;;;152    
;;;153        /* Flash 2 wait state */
;;;154        FLASH_SetLatency(FLASH_Latency_2);
000030  2002              MOVS     r0,#2
000032  f7fffffe          BL       FLASH_SetLatency
;;;155        /* Enable Prefetch Buffer */
;;;156        FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
000036  2010              MOVS     r0,#0x10
000038  f7fffffe          BL       FLASH_PrefetchBufferCmd
;;;157    
;;;158        /* PLLCLK = 8MHz * 9 = 72 MHz */
;;;159        RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
00003c  f44f11e0          MOV      r1,#0x1c0000
000040  4620              MOV      r0,r4
000042  f7fffffe          BL       RCC_PLLConfig
;;;160    
;;;161        /* Enable PLL */ 
;;;162        RCC_PLLCmd(ENABLE);
000046  2001              MOVS     r0,#1
000048  f7fffffe          BL       RCC_PLLCmd
                  |L6.76|
;;;163    
;;;164        /* Wait till PLL is ready */
;;;165        while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00004c  2039              MOVS     r0,#0x39
00004e  f7fffffe          BL       RCC_GetFlagStatus
000052  2800              CMP      r0,#0
000054  d0fa              BEQ      |L6.76|
;;;166        {
;;;167        }
;;;168    
;;;169        /* Select PLL as system clock source */
;;;170        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
000056  2002              MOVS     r0,#2
000058  f7fffffe          BL       RCC_SYSCLKConfig
                  |L6.92|
;;;171    
;;;172        /* Wait till PLL is used as system clock source */
;;;173        while(RCC_GetSYSCLKSource() != 0x08)
00005c  f7fffffe          BL       RCC_GetSYSCLKSource
000060  2808              CMP      r0,#8
000062  d1fb              BNE      |L6.92|
                  |L6.100|
;;;174        {
;;;175        }
;;;176      }
;;;177    
;;;178      /* Enable GPIOC clock,USART1 and GPIOA clock */
;;;179      RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO| RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
000064  e8bd4010          POP      {r4,lr}
000068  2101              MOVS     r1,#1
00006a  f2440015          MOV      r0,#0x4015
00006e  f7ffbffe          B.W      RCC_APB2PeriphClockCmd
;;;180    
;;;181    
;;;182    }
;;;183    
                          ENDP

000072  0000              DCW      0x0000
                  |L6.116|
                          DCD      ||.data||

                          AREA ||i.USART_Configuration||, CODE, READONLY, ALIGN=2

                  USART_Configuration PROC
;;;249    *******************************************************************************/
;;;250    void USART_Configuration(void)
000000  b530              PUSH     {r4,r5,lr}
;;;251    {
000002  b087              SUB      sp,sp,#0x1c
;;;252      USART_InitTypeDef USART_InitStructure;
;;;253      USART_ClockInitTypeDef  USART_ClockInitStructure;
;;;254    /* USART1 configuration ------------------------------------------------------*/
;;;255      /* USART1 configured as follow:
;;;256            - BaudRate = 19200 baud  
;;;257            - Word Length = 8 Bits
;;;258            - One Stop Bit
;;;259            - No parity
;;;260            - Hardware flow control disabled (RTS and CTS signals)
;;;261            - Receive and transmit enabled
;;;262            - USART Clock disabled
;;;263            - USART CPOL: Clock is active low
;;;264            - USART CPHA: Data is captured on the middle 
;;;265            - USART LastBit: The clock pulse of the last data bit is not output to 
;;;266                             the SCLK pin
;;;267      */
;;;268    USART_ClockInitStructure.USART_Clock = USART_Clock_Disable;
000004  2400              MOVS     r4,#0
;;;269    USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
;;;270    USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
000006  f44f7000          MOV      r0,#0x200
00000a  f8ad0008          STRH     r0,[sp,#8]
;;;271    USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable;
;;;272    /* Configure the USART1 synchronous paramters */
;;;273    USART_ClockInit(USART1, &USART_ClockInitStructure);
00000e  4d11              LDR      r5,|L7.84|
000010  f8ad4004          STRH     r4,[sp,#4]            ;268
000014  f8ad4006          STRH     r4,[sp,#6]            ;269
000018  f8ad400a          STRH     r4,[sp,#0xa]          ;271
00001c  a901              ADD      r1,sp,#4
00001e  4628              MOV      r0,r5
000020  f7fffffe          BL       USART_ClockInit
;;;274    
;;;275    USART_InitStructure.USART_BaudRate = 19200;
000024  f44f4096          MOV      r0,#0x4b00
;;;276    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
000028  9003              STR      r0,[sp,#0xc]
;;;277    USART_InitStructure.USART_StopBits = USART_StopBits_1;
;;;278    USART_InitStructure.USART_Parity = USART_Parity_No ;
00002a  f8ad4014          STRH     r4,[sp,#0x14]
;;;279    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
;;;280    
;;;281    
;;;282    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00002e  200c              MOVS     r0,#0xc
000030  f8ad4010          STRH     r4,[sp,#0x10]         ;276
000034  f8ad0016          STRH     r0,[sp,#0x16]
000038  f8ad4012          STRH     r4,[sp,#0x12]         ;277
00003c  f8ad4018          STRH     r4,[sp,#0x18]         ;279
;;;283    /* Configure USART1 basic and asynchronous paramters */
;;;284    USART_Init(USART1, &USART_InitStructure);
000040  a903              ADD      r1,sp,#0xc
000042  4628              MOV      r0,r5
000044  f7fffffe          BL       USART_Init
;;;285        
;;;286      /* Enable USART1 */
;;;287      USART_Cmd(USART1, ENABLE);
000048  2101              MOVS     r1,#1
00004a  4628              MOV      r0,r5
00004c  f7fffffe          BL       USART_Cmd
;;;288    }
000050  b007              ADD      sp,sp,#0x1c
000052  bd30              POP      {r4,r5,pc}
;;;289    
                          ENDP

                  |L7.84|
                          DCD      0x40013800

                          AREA ||i.WriteToBackupReg||, CODE, READONLY, ALIGN=2

                  WriteToBackupReg PROC
;;;343    *******************************************************************************/
;;;344    void WriteToBackupReg(u16 FirstBackupData)
000000  b510              PUSH     {r4,lr}
;;;345    {
;;;346      BKP_WriteBackupRegister(BKP_DR1, FirstBackupData);
000002  4601              MOV      r1,r0
000004  2004              MOVS     r0,#4
000006  f7fffffe          BL       BKP_WriteBackupRegister
00000a  4c1c              LDR      r4,|L8.124|
;;;347      BKP_WriteBackupRegister(BKP_DR2, BKP->DR1 + 0x5A);
00000c  8820              LDRH     r0,[r4,#0]
00000e  305a              ADDS     r0,r0,#0x5a
000010  b281              UXTH     r1,r0
000012  2008              MOVS     r0,#8
000014  f7fffffe          BL       BKP_WriteBackupRegister
;;;348      BKP_WriteBackupRegister(BKP_DR3, BKP->DR2 + 0x3C);
000018  88a0              LDRH     r0,[r4,#4]
00001a  303c              ADDS     r0,r0,#0x3c
00001c  b281              UXTH     r1,r0
00001e  200c              MOVS     r0,#0xc
000020  f7fffffe          BL       BKP_WriteBackupRegister
;;;349      BKP_WriteBackupRegister(BKP_DR4, BKP->DR3 + 0xA5);
000024  8920              LDRH     r0,[r4,#8]
000026  30a5              ADDS     r0,r0,#0xa5
000028  b281              UXTH     r1,r0
00002a  2010              MOVS     r0,#0x10
00002c  f7fffffe          BL       BKP_WriteBackupRegister
;;;350      BKP_WriteBackupRegister(BKP_DR5, BKP->DR4 + 0x06);
000030  89a0              LDRH     r0,[r4,#0xc]
000032  1d80              ADDS     r0,r0,#6
000034  b281              UXTH     r1,r0
000036  2014              MOVS     r0,#0x14
000038  f7fffffe          BL       BKP_WriteBackupRegister
;;;351      BKP_WriteBackupRegister(BKP_DR6, BKP->DR5 + 0x78);
00003c  8a20              LDRH     r0,[r4,#0x10]
00003e  3078              ADDS     r0,r0,#0x78
000040  b281              UXTH     r1,r0
000042  2018              MOVS     r0,#0x18
000044  f7fffffe          BL       BKP_WriteBackupRegister
;;;352      BKP_WriteBackupRegister(BKP_DR7, BKP->DR6 + 0xFF);
000048  8aa0              LDRH     r0,[r4,#0x14]
00004a  30ff              ADDS     r0,r0,#0xff
00004c  b281              UXTH     r1,r0
00004e  201c              MOVS     r0,#0x1c
000050  f7fffffe          BL       BKP_WriteBackupRegister
;;;353      BKP_WriteBackupRegister(BKP_DR8, BKP->DR7 + 0xB4);
000054  8b20              LDRH     r0,[r4,#0x18]
000056  30b4              ADDS     r0,r0,#0xb4
000058  b281              UXTH     r1,r0
00005a  2020              MOVS     r0,#0x20
00005c  f7fffffe          BL       BKP_WriteBackupRegister
;;;354      BKP_WriteBackupRegister(BKP_DR9, BKP->DR8 + 0x1E);
000060  8ba0              LDRH     r0,[r4,#0x1c]
000062  301e              ADDS     r0,r0,#0x1e
000064  b281              UXTH     r1,r0
000066  2024              MOVS     r0,#0x24
000068  f7fffffe          BL       BKP_WriteBackupRegister
;;;355      BKP_WriteBackupRegister(BKP_DR10, BKP->DR9 + 0xD4);
00006c  8c20              LDRH     r0,[r4,#0x20]
00006e  e8bd4010          POP      {r4,lr}
000072  30d4              ADDS     r0,r0,#0xd4
000074  b281              UXTH     r1,r0
000076  2028              MOVS     r0,#0x28
000078  f7ffbffe          B.W      BKP_WriteBackupRegister
;;;356    }
;;;357    
                          ENDP

                  |L8.124|
                          DCD      0x40006c04

                          AREA ||i.fputc||, CODE, READONLY, ALIGN=2

                  fputc PROC
;;;298    
;;;299    int fputc(int ch, FILE *f)
000000  b510              PUSH     {r4,lr}
;;;300    {
000002  4604              MOV      r4,r0
;;;301    #ifdef DBG_ITM
;;;302    /* PrintfݷITMĴ˿  */
;;;303      if (DEMCR & TRCENA) {
;;;304        while (ITM_Port32(0) == 0);
;;;305        ITM_Port8(0) = ch;
;;;306      }
;;;307    #else  
;;;308    /* Printfݷ */
;;;309      USART_SendData(USART1, (unsigned char) ch);
000004  b2c1              UXTB     r1,r0
000006  4805              LDR      r0,|L9.28|
000008  f7fffffe          BL       USART_SendData
;;;310      while (!(USART1->SR & USART_FLAG_TXE));
00000c  4804              LDR      r0,|L9.32|
00000e  bf00              NOP      
                  |L9.16|
000010  f8b01800          LDRH     r1,[r0,#0x800]
000014  0609              LSLS     r1,r1,#24
000016  d5fb              BPL      |L9.16|
;;;311    #endif  
;;;312      return (ch);
000018  4620              MOV      r0,r4
;;;313    }
00001a  bd10              POP      {r4,pc}
;;;314    
                          ENDP

                  |L9.28|
                          DCD      0x40013800
                  |L9.32|
                          DCD      0x40013000

                          AREA ||i.main||, CODE, READONLY, ALIGN=2

                  main PROC
;;;50     *******************************************************************************/
;;;51     int main(void)
000000  b510              PUSH     {r4,lr}
;;;52     {
;;;53     #ifdef DEBUG
;;;54       debug();
;;;55     #endif
;;;56     
;;;57       /* System Clocks Configuration */
;;;58       RCC_Configuration();
000002  f7fffffe          BL       RCC_Configuration
;;;59       
;;;60       /* NVIC configuration */
;;;61       NVIC_Configuration();
000006  f7fffffe          BL       NVIC_Configuration
;;;62         
;;;63       /* GPIO configuration */
;;;64       GPIO_Configuration();
00000a  f7fffffe          BL       GPIO_Configuration
;;;65     
;;;66       /* Configure the USART1 */
;;;67       USART_Configuration();
00000e  f7fffffe          BL       USART_Configuration
;;;68     
;;;69       printf("\n\r\n");
000012  a01c              ADR      r0,|L10.132|
000014  f7fffffe          BL       __2printf
;;;70       PrintBackupReg();
000018  f7fffffe          BL       PrintBackupReg
;;;71     
;;;72       /* Enable PWR and BKP clock */
;;;73       RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00001c  2101              MOVS     r1,#1
00001e  f04f50c0          MOV      r0,#0x18000000
000022  f7fffffe          BL       RCC_APB1PeriphClockCmd
;;;74     
;;;75       /* Enable write access to Backup domain */
;;;76       PWR_BackupAccessCmd(ENABLE);
000026  2001              MOVS     r0,#1
000028  f7fffffe          BL       PWR_BackupAccessCmd
;;;77     
;;;78       /* Clear Tamper pin Event(TE) pending flag */
;;;79       BKP_ClearFlag();
00002c  f7fffffe          BL       BKP_ClearFlag
;;;80     
;;;81       /* Tamper pin active on low level */
;;;82       BKP_TamperPinLevelConfig(BKP_TamperPinLevel_Low);
000030  2001              MOVS     r0,#1
000032  f7fffffe          BL       BKP_TamperPinLevelConfig
;;;83     
;;;84       /* Enable Tamper interrupt */
;;;85       BKP_ITConfig(ENABLE);
000036  2001              MOVS     r0,#1
000038  f7fffffe          BL       BKP_ITConfig
;;;86     
;;;87       /* Enable Tamper pin */
;;;88       BKP_TamperPinCmd(ENABLE);
00003c  2001              MOVS     r0,#1
00003e  f7fffffe          BL       BKP_TamperPinCmd
;;;89        
;;;90       /* Write data to Backup DRx registers */
;;;91     //  WriteToBackupReg(0xA53C);
;;;92     
;;;93       /* Check if the written data are correct */
;;;94     
;;;95     
;;;96       if(CheckBackupReg(0xA53C) == 0x00)
000042  f24a543c          MOV      r4,#0xa53c
000046  4620              MOV      r0,r4
000048  f7fffffe          BL       CheckBackupReg
;;;97       {
;;;98         /* Turn on led connected to PC.08 */
;;;99         GPIO_Write(GPIOC, GPIO_Pin_6);
00004c  4a0e              LDR      r2,|L10.136|
00004e  b938              CBNZ     r0,|L10.96|
000050  2140              MOVS     r1,#0x40
000052  4610              MOV      r0,r2
000054  f7fffffe          BL       GPIO_Write
;;;100    	printf("Led_1: on.--------------------The datas are as their initial status\r\n");
000058  480c              LDR      r0,|L10.140|
00005a  f7fffffe          BL       __2printf
00005e  e010              B        |L10.130|
                  |L10.96|
;;;101      }
;;;102      else
;;;103      {
;;;104        /* Turn on led connected to PC.09 */
;;;105        GPIO_Write(GPIOC, GPIO_Pin_7);
000060  2180              MOVS     r1,#0x80
000062  4610              MOV      r0,r2
000064  f7fffffe          BL       GPIO_Write
;;;106    	printf("Led_2: on.--------------------The datas have been changed.\r\n");
000068  a009              ADR      r0,|L10.144|
00006a  f7fffffe          BL       __2printf
;;;107    
;;;108        /* Clear Tamper pin Event(TE) pending flag */
;;;109        BKP_ClearFlag();
00006e  f7fffffe          BL       BKP_ClearFlag
;;;110    
;;;111    
;;;112        /* Write data to Backup DRx registers */
;;;113    	WriteToBackupReg(0xA53C);
000072  4620              MOV      r0,r4
000074  f7fffffe          BL       WriteToBackupReg
;;;114    	printf("Recover the datas of DRx to their initial status.");
000078  a015              ADR      r0,|L10.208|
00007a  f7fffffe          BL       __2printf
;;;115    	PrintBackupReg();
00007e  f7fffffe          BL       PrintBackupReg
                  |L10.130|
;;;116    
;;;117      }
;;;118            
;;;119      while(1)
000082  e7fe              B        |L10.130|
;;;120      {    
;;;121      }
;;;122    }
;;;123    
                          ENDP

                  |L10.132|
000084  0a0d0a00          DCB      "\n\r\n",0
                  |L10.136|
                          DCD      0x40011000
                  |L10.140|
                          DCD      ||.constdata||
                  |L10.144|
000090  4c65645f323a206f6e2e2d2d2d2d2d2d2d2d2d2d2d2d2d2d2d2d2d2d2d2d5468652064617461732068617665206265656e206368616e67        DCB      "Led_2: on.--------------------The datas have been chang"
0000c7  65642e0d0a00        DCB      "ed.\r\n",0
0000cd  00                DCB      0
0000ce  00                DCB      0
0000cf  00                DCB      0
                  |L10.208|
0000d0  5265636f76657220746865206461746173206f662044527820746f20746865697220696e697469616c207374617475732e00        DCB      "Recover the datas of DRx to their initial status.",0
000102  00                DCB      0
000103  00                DCB      0

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

000000  4c65645f          DCB      0x4c,0x65,0x64,0x5f
000004  313a206f          DCB      0x31,0x3a,0x20,0x6f
000008  6e2e2d2d          DCB      0x6e,0x2e,0x2d,0x2d
00000c  2d2d2d2d          DCB      0x2d,0x2d,0x2d,0x2d
000010  2d2d2d2d          DCB      0x2d,0x2d,0x2d,0x2d
000014  2d2d2d2d          DCB      0x2d,0x2d,0x2d,0x2d
000018  2d2d2d2d          DCB      0x2d,0x2d,0x2d,0x2d
00001c  2d2d5468          DCB      0x2d,0x2d,0x54,0x68
000020  65206461          DCB      0x65,0x20,0x64,0x61
000024  74617320          DCB      0x74,0x61,0x73,0x20
000028  61726520          DCB      0x61,0x72,0x65,0x20
00002c  61732074          DCB      0x61,0x73,0x20,0x74
000030  68656972          DCB      0x68,0x65,0x69,0x72
000034  20696e69          DCB      0x20,0x69,0x6e,0x69
000038  7469616c          DCB      0x74,0x69,0x61,0x6c
00003c  20737461          DCB      0x20,0x73,0x74,0x61
000040  7475730d          DCB      0x74,0x75,0x73,0x0d
000044  0a00              DCB      0x0a,0x00

                          AREA ||.data||, DATA, ALIGN=0

                  HSEStartUpStatus
000000  00                DCB      0x00

                  __ARM_use_no_argv EQU 0
