; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\output\main.o --depend=.\output\main.d --device=DARMSTM --apcs=interwork -O0 -I.\ -Id:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\main.crf main.c]
                          THUMB

                          AREA ||i.GPIO_Configuration||, CODE, READONLY, ALIGN=2

                  GPIO_Configuration PROC
;;;192    *******************************************************************************/
;;;193    void GPIO_Configuration(void)
000000  b508              PUSH     {r3,lr}
;;;194    {
;;;195      GPIO_InitTypeDef GPIO_InitStructure;
;;;196    
;;;197      /* GPIOA Configuration: Channel 1, 2, 3 and 4 Output */
;;;198      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11;
000002  f44f6070          MOV      r0,#0xf00
000006  f8ad0000          STRH     r0,[sp,#0]
;;;199      GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00000a  2018              MOVS     r0,#0x18
00000c  f88d0003          STRB     r0,[sp,#3]
;;;200      GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
000010  2003              MOVS     r0,#3
000012  f88d0002          STRB     r0,[sp,#2]
;;;201      GPIO_Init(GPIOA, &GPIO_InitStructure);
000016  4669              MOV      r1,sp
000018  480b              LDR      r0,|L1.72|
00001a  f7fffffe          BL       GPIO_Init
;;;202    
;;;203      /* GPIOB Configuration: Channel 1N, 2N and 3N Output */
;;;204      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
00001e  f44f4060          MOV      r0,#0xe000
000022  f8ad0000          STRH     r0,[sp,#0]
;;;205      GPIO_Init(GPIOB, &GPIO_InitStructure); 
000026  4669              MOV      r1,sp
000028  4808              LDR      r0,|L1.76|
00002a  f7fffffe          BL       GPIO_Init
;;;206      
;;;207      /* GPIOB Configuration: BKIN pin */   
;;;208      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
00002e  f44f5080          MOV      r0,#0x1000
000032  f8ad0000          STRH     r0,[sp,#0]
;;;209      GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
000036  2004              MOVS     r0,#4
000038  f88d0003          STRB     r0,[sp,#3]
;;;210      GPIO_Init(GPIOB, &GPIO_InitStructure);
00003c  4669              MOV      r1,sp
00003e  4803              LDR      r0,|L1.76|
000040  f7fffffe          BL       GPIO_Init
;;;211    }
000044  bd08              POP      {r3,pc}
;;;212    
                          ENDP

000046  0000              DCW      0x0000
                  |L1.72|
                          DCD      0x40010800
                  |L1.76|
                          DCD      0x40010c00

                          AREA ||i.NVIC_Configuration||, CODE, READONLY, ALIGN=1

                  NVIC_Configuration PROC
;;;219    *******************************************************************************/
;;;220    void NVIC_Configuration(void)
000000  b510              PUSH     {r4,lr}
;;;221    {  
;;;222    #ifdef  VECT_TAB_RAM  
;;;223      /* Set the Vector Table base location at 0x20000000 */ 
;;;224      NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); 
;;;225    #else  /* VECT_TAB_FLASH  */
;;;226      /* Set the Vector Table base location at 0x08000000 */ 
;;;227      NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);   
000002  2100              MOVS     r1,#0
000004  f04f6000          MOV      r0,#0x8000000
000008  f7fffffe          BL       NVIC_SetVectorTable
;;;228    #endif
;;;229    }
00000c  bd10              POP      {r4,pc}
;;;230    
                          ENDP


                          AREA ||i.RCC_Configuration||, CODE, READONLY, ALIGN=2

                  RCC_Configuration PROC
;;;133    *******************************************************************************/
;;;134    void RCC_Configuration(void)
000000  b510              PUSH     {r4,lr}
;;;135    {   
;;;136      /* RCC system reset(for debug purpose) */
;;;137      RCC_DeInit();
000002  f7fffffe          BL       RCC_DeInit
;;;138    
;;;139      /* Enable HSE */
;;;140      RCC_HSEConfig(RCC_HSE_ON);
000006  f44f3080          MOV      r0,#0x10000
00000a  f7fffffe          BL       RCC_HSEConfig
;;;141    
;;;142      /* Wait till HSE is ready */
;;;143      HSEStartUpStatus = RCC_WaitForHSEStartUp();
00000e  f7fffffe          BL       RCC_WaitForHSEStartUp
000012  4919              LDR      r1,|L3.120|
000014  7008              STRB     r0,[r1,#0]
;;;144    
;;;145      if(HSEStartUpStatus == SUCCESS)
000016  4608              MOV      r0,r1
000018  7800              LDRB     r0,[r0,#0]  ; HSEStartUpStatus
00001a  2801              CMP      r0,#1
00001c  d126              BNE      |L3.108|
;;;146      {
;;;147        /* HCLK = SYSCLK */
;;;148        RCC_HCLKConfig(RCC_SYSCLK_Div1); 
00001e  2000              MOVS     r0,#0
000020  f7fffffe          BL       RCC_HCLKConfig
;;;149      
;;;150        /* PCLK2 = HCLK */
;;;151        RCC_PCLK2Config(RCC_HCLK_Div1); 
000024  2000              MOVS     r0,#0
000026  f7fffffe          BL       RCC_PCLK2Config
;;;152    
;;;153        /* PCLK1 = HCLK/2 */
;;;154        RCC_PCLK1Config(RCC_HCLK_Div2);
00002a  f44f6080          MOV      r0,#0x400
00002e  f7fffffe          BL       RCC_PCLK1Config
;;;155    
;;;156        /* Flash 2 wait state */
;;;157        FLASH_SetLatency(FLASH_Latency_2);
000032  2002              MOVS     r0,#2
000034  f7fffffe          BL       FLASH_SetLatency
;;;158        /* Enable Prefetch Buffer */
;;;159        FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
000038  2010              MOVS     r0,#0x10
00003a  f7fffffe          BL       FLASH_PrefetchBufferCmd
;;;160    
;;;161        /* PLLCLK = 8MHz * 9 = 72 MHz */
;;;162        RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
00003e  f44f11e0          MOV      r1,#0x1c0000
000042  f44f3080          MOV      r0,#0x10000
000046  f7fffffe          BL       RCC_PLLConfig
;;;163    
;;;164        /* Enable PLL */ 
;;;165        RCC_PLLCmd(ENABLE);
00004a  2001              MOVS     r0,#1
00004c  f7fffffe          BL       RCC_PLLCmd
;;;166    
;;;167        /* Wait till PLL is ready */
;;;168        while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
000050  bf00              NOP      
                  |L3.82|
000052  2039              MOVS     r0,#0x39
000054  f7fffffe          BL       RCC_GetFlagStatus
000058  2800              CMP      r0,#0
00005a  d0fa              BEQ      |L3.82|
;;;169        {
;;;170        }
;;;171    
;;;172        /* Select PLL as system clock source */
;;;173        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00005c  2002              MOVS     r0,#2
00005e  f7fffffe          BL       RCC_SYSCLKConfig
;;;174    
;;;175        /* Wait till PLL is used as system clock source */
;;;176        while(RCC_GetSYSCLKSource() != 0x08)
000062  bf00              NOP      
                  |L3.100|
000064  f7fffffe          BL       RCC_GetSYSCLKSource
000068  2808              CMP      r0,#8
00006a  d1fb              BNE      |L3.100|
                  |L3.108|
;;;177        {
;;;178        }
;;;179      }
;;;180    
;;;181      /* TIM1, GPIOA and GPIOB clock enable */
;;;182      RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA |
00006c  2101              MOVS     r1,#1
00006e  f640000c          MOV      r0,#0x80c
000072  f7fffffe          BL       RCC_APB2PeriphClockCmd
;;;183                             RCC_APB2Periph_GPIOB, ENABLE);
;;;184    }
000076  bd10              POP      {r4,pc}
;;;185    
                          ENDP

                  |L3.120|
                          DCD      HSEStartUpStatus

                          AREA ||i.main||, CODE, READONLY, ALIGN=2

                  main PROC
;;;37     *******************************************************************************/
;;;38     int main(void)
000000  b510              PUSH     {r4,lr}
;;;39     {
;;;40     #ifdef DEBUG
;;;41       debug();
;;;42     #endif
;;;43     
;;;44       /* System Clocks Configuration */
;;;45       RCC_Configuration();
000002  f7fffffe          BL       RCC_Configuration
;;;46     
;;;47       /* GPIO Configuration */
;;;48       GPIO_Configuration();
000006  f7fffffe          BL       GPIO_Configuration
;;;49     
;;;50       /* NVIC configuration */
;;;51       NVIC_Configuration();
00000a  f7fffffe          BL       NVIC_Configuration
;;;52     
;;;53       /* -----------------------------------------------------------------------
;;;54       TIM1 Configuration to:
;;;55     
;;;56       1/ Generate 3 complementary PWM signals with 3 different duty cycles:
;;;57       TIM1CLK = 72 MHz, Prescaler = 0x0, TIM1 counter clock = 72 MHz
;;;58       TIM1 frequency = TIM1CLK/(TIM1_Period + 1) = 1.098 KHz
;;;59     
;;;60       TIM1 Channel1 duty cycle = TIM1->CCR1 / TIM1_Period = 50% 
;;;61       TIM1 Channel1N duty cycle = (TIM1_Period - TIM1_CCR1) / (TIM1_Period + 1) = 50%
;;;62     
;;;63       TIM1 Channel2 duty cycle = TIM1_CCR2 / TIM1_Period = 25%
;;;64       TIM1 Channel2N duty cycle = (TIM1_Period - TIM1_CCR1) / (TIM1_Period + 1) = 75% 
;;;65     
;;;66       TIM1 Channel3 duty cycle = TIM1_CCR3 / TIM1_Period = 12.5% 
;;;67       TIM1 Channel3N duty cycle = (TIM1_Period - TIM1_CCR3) / (TIM1_Period + 1) = 87.5% 
;;;68     
;;;69       2/ Insert a dead time equal to 1.62 us
;;;70       3/ Configure the break feature, active at High level, and using the automatic 
;;;71          output enable feature
;;;72       4/ Use the Locking parametres level1. 
;;;73       ----------------------------------------------------------------------- */
;;;74     
;;;75       /* TIM1 Peripheral Configuration */ 
;;;76       TIM_DeInit(TIM1);
00000e  4828              LDR      r0,|L4.176|
000010  f7fffffe          BL       TIM_DeInit
;;;77     
;;;78       /* Time Base configuration */
;;;79       TIM1_TimeBaseStructure.TIM_Prescaler = 0x0;
000014  2000              MOVS     r0,#0
000016  4927              LDR      r1,|L4.180|
000018  8008              STRH     r0,[r1,#0]
;;;80       TIM1_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00001a  8048              STRH     r0,[r1,#2]
;;;81       TIM1_TimeBaseStructure.TIM_Period = 0xFFFF;
00001c  f64f70ff          MOV      r0,#0xffff
000020  8088              STRH     r0,[r1,#4]
;;;82       TIM1_TimeBaseStructure.TIM_ClockDivision = 0x0;
000022  2000              MOVS     r0,#0
000024  80c8              STRH     r0,[r1,#6]
;;;83       TIM1_TimeBaseStructure.TIM_RepetitionCounter = 0x0;
000026  7208              STRB     r0,[r1,#8]
;;;84     
;;;85       TIM_TimeBaseInit(TIM1,&TIM1_TimeBaseStructure);
000028  4821              LDR      r0,|L4.176|
00002a  f7fffffe          BL       TIM_TimeBaseInit
;;;86     
;;;87       /* Channel 1, 2,3 and 4 Configuration in PWM mode */
;;;88       TIM1_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; 
00002e  2070              MOVS     r0,#0x70
000030  4921              LDR      r1,|L4.184|
000032  8008              STRH     r0,[r1,#0]
;;;89       TIM1_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; 
000034  2001              MOVS     r0,#1
000036  8048              STRH     r0,[r1,#2]
;;;90       TIM1_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;                  
000038  2004              MOVS     r0,#4
00003a  8088              STRH     r0,[r1,#4]
;;;91       TIM1_OCInitStructure.TIM_Pulse = CCR1_Val; 
00003c  481f              LDR      r0,|L4.188|
00003e  8800              LDRH     r0,[r0,#0]  ; CCR1_Val
000040  80c8              STRH     r0,[r1,#6]
;;;92       TIM1_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; 
000042  2002              MOVS     r0,#2
000044  8108              STRH     r0,[r1,#8]
;;;93       TIM1_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;         
000046  2008              MOVS     r0,#8
000048  8148              STRH     r0,[r1,#0xa]
;;;94       TIM1_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00004a  0140              LSLS     r0,r0,#5
00004c  8188              STRH     r0,[r1,#0xc]
;;;95       TIM1_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;          
00004e  2000              MOVS     r0,#0
000050  81c8              STRH     r0,[r1,#0xe]
;;;96       
;;;97       TIM_OC1Init(TIM1,&TIM1_OCInitStructure); 
000052  4817              LDR      r0,|L4.176|
000054  f7fffffe          BL       TIM_OC1Init
;;;98     
;;;99       TIM1_OCInitStructure.TIM_Pulse = CCR2_Val;
000058  4819              LDR      r0,|L4.192|
00005a  8800              LDRH     r0,[r0,#0]  ; CCR2_Val
00005c  4916              LDR      r1,|L4.184|
00005e  80c8              STRH     r0,[r1,#6]
;;;100      TIM_OC2Init(TIM1,&TIM1_OCInitStructure);
000060  4813              LDR      r0,|L4.176|
000062  f7fffffe          BL       TIM_OC2Init
;;;101    
;;;102      TIM1_OCInitStructure.TIM_Pulse = CCR3_Val;
000066  4817              LDR      r0,|L4.196|
000068  8800              LDRH     r0,[r0,#0]  ; CCR3_Val
00006a  4913              LDR      r1,|L4.184|
00006c  80c8              STRH     r0,[r1,#6]
;;;103      TIM_OC3Init(TIM1,&TIM1_OCInitStructure);
00006e  4810              LDR      r0,|L4.176|
000070  f7fffffe          BL       TIM_OC3Init
;;;104    
;;;105      /* Automatic Output enable, Break, dead time and lock configuration*/
;;;106      TIM1_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
000074  f44f6000          MOV      r0,#0x800
000078  4913              LDR      r1,|L4.200|
00007a  8008              STRH     r0,[r1,#0]
;;;107      TIM1_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
00007c  1040              ASRS     r0,r0,#1
00007e  8048              STRH     r0,[r1,#2]
;;;108      TIM1_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1; 
000080  1080              ASRS     r0,r0,#2
000082  8088              STRH     r0,[r1,#4]
;;;109      TIM1_BDTRInitStructure.TIM_DeadTime = 0x75;
000084  2075              MOVS     r0,#0x75
000086  80c8              STRH     r0,[r1,#6]
;;;110      TIM1_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
000088  f44f5080          MOV      r0,#0x1000
00008c  8108              STRH     r0,[r1,#8]
;;;111      TIM1_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
00008e  0040              LSLS     r0,r0,#1
000090  8148              STRH     r0,[r1,#0xa]
;;;112      TIM1_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
000092  0040              LSLS     r0,r0,#1
000094  8188              STRH     r0,[r1,#0xc]
;;;113    
;;;114      TIM_BDTRConfig(TIM1,&TIM1_BDTRInitStructure);
000096  4806              LDR      r0,|L4.176|
000098  f7fffffe          BL       TIM_BDTRConfig
;;;115    
;;;116      /* TIM1 counter enable */
;;;117      TIM_Cmd(TIM1,ENABLE);
00009c  2101              MOVS     r1,#1
00009e  4804              LDR      r0,|L4.176|
0000a0  f7fffffe          BL       TIM_Cmd
;;;118    
;;;119      /* Main Output Enable */
;;;120      TIM_CtrlPWMOutputs(TIM1,ENABLE);
0000a4  2101              MOVS     r1,#1
0000a6  4802              LDR      r0,|L4.176|
0000a8  f7fffffe          BL       TIM_CtrlPWMOutputs
;;;121      
;;;122      while(1)
0000ac  bf00              NOP      
                  |L4.174|
0000ae  e7fe              B        |L4.174|
;;;123      {
;;;124      }    
;;;125    }
;;;126    
                          ENDP

                  |L4.176|
                          DCD      0x40012c00
                  |L4.180|
                          DCD      TIM1_TimeBaseStructure
                  |L4.184|
                          DCD      TIM1_OCInitStructure
                  |L4.188|
                          DCD      CCR1_Val
                  |L4.192|
                          DCD      CCR2_Val
                  |L4.196|
                          DCD      CCR3_Val
                  |L4.200|
                          DCD      TIM1_BDTRInitStructure

                          AREA ||.bss||, DATA, NOINIT, ALIGN=1

                  TIM1_TimeBaseStructure
                          %        10
                  TIM1_OCInitStructure
                          %        16
                  TIM1_BDTRInitStructure
                          %        14

                          AREA ||.data||, DATA, ALIGN=1

                  capture
000000  0000              DCW      0x0000
                  CCR1_Val
000002  7fff              DCW      0x7fff
                  CCR2_Val
000004  3fff              DCW      0x3fff
                  CCR3_Val
000006  1fff              DCW      0x1fff
                  HSEStartUpStatus
000008  00                DCB      0x00

                  __ARM_use_no_argv EQU 0
