; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\output\main.o --depend=.\output\main.d --device=DARMSTM --apcs=interwork -O3 -I.\ -Id:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\main.crf main.c]
                          THUMB

                          AREA ||i.Buffercmp||, CODE, READONLY, ALIGN=1

                  Buffercmp PROC
;;;278    *******************************************************************************/
;;;279    BitAction Buffercmp(u8* pBuffer1, u8* pBuffer2, u16 BufferLength)
000000  b510              PUSH     {r4,lr}
;;;280    {
;;;281      while(BufferLength--)
;;;282      {
;;;283        if(*pBuffer1 != *pBuffer2)
;;;284        {
;;;285          return  Bit_RESET;
;;;286        }
;;;287        
;;;288        pBuffer1++;
;;;289        pBuffer2++;
000002  e007              B        |L1.20|
                  |L1.4|
000004  7803              LDRB     r3,[r0,#0]            ;283
000006  780c              LDRB     r4,[r1,#0]            ;283
000008  42a3              CMP      r3,r4                 ;283
00000a  d001              BEQ      |L1.16|
00000c  2000              MOVS     r0,#0                 ;285
;;;290      }
;;;291    
;;;292      return Bit_SET;
;;;293    }
00000e  bd10              POP      {r4,pc}
                  |L1.16|
000010  1c40              ADDS     r0,r0,#1              ;288
000012  1c49              ADDS     r1,r1,#1              ;289
                  |L1.20|
000014  0013              MOVS     r3,r2                 ;281
000016  f1a20201          SUB      r2,r2,#1              ;281
00001a  b292              UXTH     r2,r2                 ;281
00001c  d1f2              BNE      |L1.4|
00001e  2001              MOVS     r0,#1                 ;292
000020  bd10              POP      {r4,pc}
;;;294    
                          ENDP


                          AREA ||i.GPIO_Configuration||, CODE, READONLY, ALIGN=2

                  GPIO_Configuration PROC
;;;231    *******************************************************************************/
;;;232    void GPIO_Configuration(void)
000000  b538              PUSH     {r3-r5,lr}
;;;233    {
;;;234      GPIO_InitTypeDef GPIO_InitStructure;
;;;235    
;;;236      /* Configure SPI1 pins: SCK, MISO and MOSI ---------------------------------*/
;;;237      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
000002  20e0              MOVS     r0,#0xe0
000004  f8ad0000          STRH     r0,[sp,#0]
;;;238      GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
000008  2403              MOVS     r4,#3
00000a  f88d4002          STRB     r4,[sp,#2]
;;;239      GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00000e  2018              MOVS     r0,#0x18
000010  f88d0003          STRB     r0,[sp,#3]
;;;240      GPIO_Init(GPIOA, &GPIO_InitStructure);
000014  4669              MOV      r1,sp
000016  480d              LDR      r0,|L2.76|
000018  f7fffffe          BL       GPIO_Init
;;;241    
;;;242      /* Configure SPI2 pins: SCK, MISO and MOSI ---------------------------------*/
;;;243      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
00001c  f44f4060          MOV      r0,#0xe000
;;;244      GPIO_Init(GPIOC, &GPIO_InitStructure);
000020  4d0b              LDR      r5,|L2.80|
000022  f8ad0000          STRH     r0,[sp,#0]            ;243
000026  4669              MOV      r1,sp
000028  4628              MOV      r0,r5
00002a  f7fffffe          BL       GPIO_Init
;;;245    
;;;246      GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_6 | GPIO_Pin_7;
00002e  f44f7070          MOV      r0,#0x3c0
000032  f8ad0000          STRH     r0,[sp,#0]
;;;247      GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
000036  f88d4002          STRB     r4,[sp,#2]
;;;248      GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00003a  2010              MOVS     r0,#0x10
00003c  f88d0003          STRB     r0,[sp,#3]
;;;249      GPIO_Init(GPIOC, &GPIO_InitStructure);
000040  4669              MOV      r1,sp
000042  4628              MOV      r0,r5
000044  f7fffffe          BL       GPIO_Init
;;;250    }
000048  bd38              POP      {r3-r5,pc}
;;;251    
                          ENDP

00004a  0000              DCW      0x0000
                  |L2.76|
                          DCD      0x40010800
                  |L2.80|
                          DCD      0x40011000

                          AREA ||i.NVIC_Configuration||, CODE, READONLY, ALIGN=1

                  NVIC_Configuration PROC
;;;258    *******************************************************************************/
;;;259    void NVIC_Configuration(void)
000000  2100              MOVS     r1,#0
;;;260    {
;;;261    #ifdef  VECT_TAB_RAM  
;;;262      /* Set the Vector Table base location at 0x20000000 */ 
;;;263      NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); 
;;;264    #else  /* VECT_TAB_FLASH  */
;;;265      /* Set the Vector Table base location at 0x08000000 */ 
;;;266      NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);   
000002  f04f6000          MOV      r0,#0x8000000
000006  f7ffbffe          B.W      NVIC_SetVectorTable
;;;267    #endif
;;;268    }
;;;269    
                          ENDP


                          AREA ||i.RCC_Configuration||, CODE, READONLY, ALIGN=2

                  RCC_Configuration PROC
;;;169    *******************************************************************************/
;;;170    void RCC_Configuration(void)
000000  b570              PUSH     {r4-r6,lr}
;;;171    {
;;;172      /* RCC system reset(for debug purpose) */
;;;173      RCC_DeInit();
000002  f7fffffe          BL       RCC_DeInit
;;;174    
;;;175      /* Enable HSE */
;;;176      RCC_HSEConfig(RCC_HSE_ON);
000006  f44f3480          MOV      r4,#0x10000
00000a  4620              MOV      r0,r4
00000c  f7fffffe          BL       RCC_HSEConfig
;;;177    
;;;178      /* Wait till HSE is ready */
;;;179      HSEStartUpStatus = RCC_WaitForHSEStartUp();
000010  f7fffffe          BL       RCC_WaitForHSEStartUp
000014  491a              LDR      r1,|L4.128|
000016  71c8              STRB     r0,[r1,#7]
;;;180    
;;;181      if(HSEStartUpStatus == SUCCESS)
000018  b2c0              UXTB     r0,r0
00001a  2801              CMP      r0,#1
00001c  d124              BNE      |L4.104|
;;;182      {
;;;183        /* HCLK = SYSCLK */
;;;184        RCC_HCLKConfig(RCC_SYSCLK_Div1); 
00001e  2000              MOVS     r0,#0
000020  f7fffffe          BL       RCC_HCLKConfig
;;;185      
;;;186        /* PCLK2 = HCLK/2 */
;;;187        RCC_PCLK2Config(RCC_HCLK_Div2); 
000024  11a5              ASRS     r5,r4,#6
000026  4628              MOV      r0,r5
000028  f7fffffe          BL       RCC_PCLK2Config
;;;188    
;;;189        /* PCLK1 = HCLK/2 */
;;;190        RCC_PCLK1Config(RCC_HCLK_Div2);
00002c  4628              MOV      r0,r5
00002e  f7fffffe          BL       RCC_PCLK1Config
;;;191     
;;;192        /* Flash 2 wait state */
;;;193        FLASH_SetLatency(FLASH_Latency_2);
000032  2002              MOVS     r0,#2
000034  f7fffffe          BL       FLASH_SetLatency
;;;194        /* Enable Prefetch Buffer */
;;;195        FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
000038  2010              MOVS     r0,#0x10
00003a  f7fffffe          BL       FLASH_PrefetchBufferCmd
;;;196    
;;;197        /* PLLCLK = 8MHz * 9 = 72 MHz */
;;;198        RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
00003e  f44f11e0          MOV      r1,#0x1c0000
000042  4620              MOV      r0,r4
000044  f7fffffe          BL       RCC_PLLConfig
;;;199    
;;;200        /* Enable PLL */ 
;;;201        RCC_PLLCmd(ENABLE);
000048  2001              MOVS     r0,#1
00004a  f7fffffe          BL       RCC_PLLCmd
                  |L4.78|
;;;202    
;;;203        /* Wait till PLL is ready */
;;;204        while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00004e  2039              MOVS     r0,#0x39
000050  f7fffffe          BL       RCC_GetFlagStatus
000054  2800              CMP      r0,#0
000056  d0fa              BEQ      |L4.78|
;;;205        {
;;;206        }
;;;207    
;;;208        /* Select PLL as system clock source */
;;;209        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
000058  2002              MOVS     r0,#2
00005a  f7fffffe          BL       RCC_SYSCLKConfig
;;;210    
;;;211        /* Wait till PLL is used as system clock source */
;;;212        while(RCC_GetSYSCLKSource() != 0x08)
00005e  bf00              NOP      
                  |L4.96|
000060  f7fffffe          BL       RCC_GetSYSCLKSource
000064  2808              CMP      r0,#8
000066  d1fb              BNE      |L4.96|
                  |L4.104|
;;;213        {
;;;214        }
;;;215      }
;;;216    
;;;217    /* Enable peripheral clocks --------------------------------------------------*/
;;;218      /* GPIOA, GPIOC and SPI1 clock enable */
;;;219      RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC |
000068  2101              MOVS     r1,#1
00006a  f2410014          MOV      r0,#0x1014
00006e  f7fffffe          BL       RCC_APB2PeriphClockCmd
;;;220                             RCC_APB2Periph_SPI1, ENABLE);
;;;221      /* SPI2 Periph clock enable */
;;;222      RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
000072  e8bd4070          POP      {r4-r6,lr}
000076  2101              MOVS     r1,#1
000078  0388              LSLS     r0,r1,#14
00007a  f7ffbffe          B.W      RCC_APB1PeriphClockCmd
;;;223    }
;;;224    
                          ENDP

00007e  0000              DCW      0x0000
                  |L4.128|
                          DCD      ||.data||

                          AREA ||i.main||, CODE, READONLY, ALIGN=2

                  main PROC
;;;47     *******************************************************************************/
;;;48     int main(void)
000000  e92d5ff0          PUSH     {r4-r12,lr}
;;;49     {
;;;50     #ifdef DEBUG
;;;51       debug();
;;;52     #endif
;;;53     
;;;54       /* System clocks configuration ---------------------------------------------*/
;;;55       RCC_Configuration();
000004  f7fffffe          BL       RCC_Configuration
;;;56     
;;;57       /* NVIC configuration ------------------------------------------------------*/
;;;58       NVIC_Configuration();
000008  f7fffffe          BL       NVIC_Configuration
;;;59     
;;;60       /* GPIO configuration ------------------------------------------------------*/
;;;61       GPIO_Configuration();
00000c  f7fffffe          BL       GPIO_Configuration
;;;62     
;;;63       /* 1st phase: SPI1 Master and SPI2 Slave */
;;;64       /* SPI1 Config -------------------------------------------------------------*/
;;;65       SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
000010  4c7a              LDR      r4,|L5.508|
000012  f04f0800          MOV      r8,#0
000016  f8a48000          STRH     r8,[r4,#0]
;;;66       SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00001a  f44f7082          MOV      r0,#0x104
00001e  8060              STRH     r0,[r4,#2]
;;;67       SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
000020  f8a48004          STRH     r8,[r4,#4]
;;;68       SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
000024  f8a48006          STRH     r8,[r4,#6]
;;;69       SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
000028  2001              MOVS     r0,#1
00002a  8120              STRH     r0,[r4,#8]
;;;70       SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00002c  0240              LSLS     r0,r0,#9
00002e  8160              STRH     r0,[r4,#0xa]
;;;71       SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
000030  2008              MOVS     r0,#8
000032  81a0              STRH     r0,[r4,#0xc]
;;;72       SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB;
000034  2080              MOVS     r0,#0x80
000036  81e0              STRH     r0,[r4,#0xe]
;;;73       SPI_InitStructure.SPI_CRCPolynomial = 7;
000038  2007              MOVS     r0,#7
;;;74       SPI_Init(SPI1, &SPI_InitStructure);
00003a  4e71              LDR      r6,|L5.512|
00003c  8220              STRH     r0,[r4,#0x10]         ;73
00003e  4645              MOV      r5,r8                 ;65
000040  4621              MOV      r1,r4
000042  4630              MOV      r0,r6
000044  f7fffffe          BL       SPI_Init
;;;75     
;;;76       /* SPI2 Config -------------------------------------------------------------*/
;;;77       SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
;;;78       SPI_Init(SPI2, &SPI_InitStructure);
000048  4f6e              LDR      r7,|L5.516|
00004a  8065              STRH     r5,[r4,#2]            ;77
00004c  4621              MOV      r1,r4
00004e  4638              MOV      r0,r7
000050  f7fffffe          BL       SPI_Init
;;;79     
;;;80       /* Enable SPI1 */
;;;81       SPI_Cmd(SPI1, ENABLE);
000054  2101              MOVS     r1,#1
000056  4630              MOV      r0,r6
000058  f7fffffe          BL       SPI_Cmd
;;;82       /* Enable SPI2 */
;;;83       SPI_Cmd(SPI2, ENABLE);
00005c  2101              MOVS     r1,#1
00005e  4638              MOV      r0,r7
000060  f7fffffe          BL       SPI_Cmd
;;;84     
;;;85       /* Transfer procedure */
;;;86       while(Tx_Idx<BufferSize)
;;;87       { 
;;;88         /* Wait for SPI1 Tx buffer empty */ 
;;;89         while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE)==RESET);
;;;90         /* Send SPI2 data */ 
;;;91         SPI_I2S_SendData(SPI2, SPI2_Buffer_Tx[Tx_Idx]);	
000064  f8df91a0          LDR      r9,|L5.520|
;;;92         /* Send SPI1 data */ 
;;;93         SPI_I2S_SendData(SPI1, SPI1_Buffer_Tx[Tx_Idx++]);     
;;;94         /* Wait for SPI2 data reception */
;;;95         while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE)==RESET);
;;;96         /* Read SPI2 received data */ 
;;;97         SPI2_Buffer_Rx[Rx_Idx] = SPI_I2S_ReceiveData(SPI2);
;;;98         /* Wait for SPI1 data reception */ 
;;;99         while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE)==RESET);
;;;100        /* Read SPI1 received data */ 
;;;101        SPI1_Buffer_Rx[Rx_Idx++] = SPI_I2S_ReceiveData(SPI1);		 
000068  f1040512          ADD      r5,r4,#0x12
00006c  f1a90a20          SUB      r10,r9,#0x20          ;93
000070  f1040b32          ADD      r11,r4,#0x32          ;97
000074  f1a90628          SUB      r6,r9,#0x28           ;91
000078  e02d              B        |L5.214|
                  |L5.122|
00007a  4c61              LDR      r4,|L5.512|
                  |L5.124|
00007c  2102              MOVS     r1,#2                 ;89
00007e  4620              MOV      r0,r4                 ;89
000080  f7fffffe          BL       SPI_I2S_GetFlagStatus
000084  2800              CMP      r0,#0                 ;89
000086  d0f9              BEQ      |L5.124|
000088  7831              LDRB     r1,[r6,#0]            ;91  ; Tx_Idx
00008a  4638              MOV      r0,r7                 ;91
00008c  f8191001          LDRB     r1,[r9,r1]            ;91
000090  f7fffffe          BL       SPI_I2S_SendData
000094  7830              LDRB     r0,[r6,#0]            ;93  ; Tx_Idx
000096  f81a1000          LDRB     r1,[r10,r0]           ;93
00009a  1c40              ADDS     r0,r0,#1              ;93
00009c  7030              STRB     r0,[r6,#0]            ;93
00009e  4620              MOV      r0,r4                 ;93
0000a0  f7fffffe          BL       SPI_I2S_SendData
                  |L5.164|
0000a4  2101              MOVS     r1,#1                 ;95
0000a6  4638              MOV      r0,r7                 ;95
0000a8  f7fffffe          BL       SPI_I2S_GetFlagStatus
0000ac  2800              CMP      r0,#0                 ;95
0000ae  d0f9              BEQ      |L5.164|
0000b0  4638              MOV      r0,r7                 ;97
0000b2  f7fffffe          BL       SPI_I2S_ReceiveData
0000b6  7872              LDRB     r2,[r6,#1]            ;97  ; Rx_Idx
0000b8  f80b0002          STRB     r0,[r11,r2]           ;97
                  |L5.188|
0000bc  2101              MOVS     r1,#1                 ;99
0000be  4620              MOV      r0,r4                 ;99
0000c0  f7fffffe          BL       SPI_I2S_GetFlagStatus
0000c4  2800              CMP      r0,#0                 ;99
0000c6  d0f9              BEQ      |L5.188|
0000c8  4620              MOV      r0,r4
0000ca  f7fffffe          BL       SPI_I2S_ReceiveData
0000ce  7871              LDRB     r1,[r6,#1]  ; Rx_Idx
0000d0  5468              STRB     r0,[r5,r1]
0000d2  1c49              ADDS     r1,r1,#1
0000d4  7071              STRB     r1,[r6,#1]
                  |L5.214|
0000d6  7830              LDRB     r0,[r6,#0]            ;86  ; Tx_Idx
0000d8  2820              CMP      r0,#0x20              ;86
0000da  d3ce              BCC      |L5.122|
;;;102      }
;;;103    
;;;104      /* Check the corectness of written dada */
;;;105      TransferStatus1 = Buffercmp(SPI2_Buffer_Rx, SPI1_Buffer_Tx, BufferSize);
0000dc  494a              LDR      r1,|L5.520|
0000de  4847              LDR      r0,|L5.508|
0000e0  2220              MOVS     r2,#0x20
0000e2  3920              SUBS     r1,r1,#0x20
0000e4  3032              ADDS     r0,r0,#0x32
0000e6  f7fffffe          BL       Buffercmp
0000ea  70f0              STRB     r0,[r6,#3]
;;;106      TransferStatus2 = Buffercmp(SPI1_Buffer_Rx, SPI2_Buffer_Tx, BufferSize);
0000ec  4843              LDR      r0,|L5.508|
0000ee  2220              MOVS     r2,#0x20
0000f0  4945              LDR      r1,|L5.520|
0000f2  3012              ADDS     r0,r0,#0x12
0000f4  f7fffffe          BL       Buffercmp
0000f8  7130              STRB     r0,[r6,#4]
;;;107      GPIO_WriteBit(GPIOC, GPIO_Pin_6, TransferStatus1);
0000fa  4c44              LDR      r4,|L5.524|
0000fc  78f2              LDRB     r2,[r6,#3]  ; TransferStatus1
0000fe  2140              MOVS     r1,#0x40
000100  4620              MOV      r0,r4
000102  f7fffffe          BL       GPIO_WriteBit
;;;108      GPIO_WriteBit(GPIOC, GPIO_Pin_7, TransferStatus2);
000106  7932              LDRB     r2,[r6,#4]  ; TransferStatus2
000108  2180              MOVS     r1,#0x80
00010a  4620              MOV      r0,r4
00010c  f7fffffe          BL       GPIO_WriteBit
;;;109      /* TransferStatus1, TransferStatus2 = PASSED, if the transmitted and received data
;;;110         are equal */
;;;111      /* TransferStatus1, TransferStatus2 = FAILED, if the transmitted and received data
;;;112         are different */
;;;113    
;;;114      /* 2nd phase: SPI1 Slave and SPI2 Master */  
;;;115      /* SPI1 Re-configuration ---------------------------------------------------*/
;;;116      SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
000110  4c3a              LDR      r4,|L5.508|
;;;117      SPI_Init(SPI1, &SPI_InitStructure);
000112  483b              LDR      r0,|L5.512|
000114  f8a48002          STRH     r8,[r4,#2]            ;116
000118  4621              MOV      r1,r4
00011a  f7fffffe          BL       SPI_Init
;;;118    
;;;119      /* SPI2 Re-configuration ---------------------------------------------------*/
;;;120      SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00011e  f44f7182          MOV      r1,#0x104
000122  8061              STRH     r1,[r4,#2]
;;;121      SPI_Init(SPI2, &SPI_InitStructure);
000124  4621              MOV      r1,r4
000126  4638              MOV      r0,r7
000128  f7fffffe          BL       SPI_Init
;;;122    
;;;123      /* Reset Tx_Idx, Rx_Idx indexes and receive tables values */
;;;124      Tx_Idx=0;
00012c  f8868000          STRB     r8,[r6,#0]
;;;125      Rx_Idx=0;
000130  f8868001          STRB     r8,[r6,#1]
;;;126      for(k=0; k<BufferSize; k++)  SPI2_Buffer_Rx[k]=0;
000134  f8868002          STRB     r8,[r6,#2]
000138  465c              MOV      r4,r11                ;97
                  |L5.314|
00013a  78b0              LDRB     r0,[r6,#2]  ; k
00013c  1c41              ADDS     r1,r0,#1
00013e  b2c9              UXTB     r1,r1
000140  f8048000          STRB     r8,[r4,r0]
000144  70b1              STRB     r1,[r6,#2]
000146  2920              CMP      r1,#0x20
000148  d3f7              BCC      |L5.314|
;;;127      for(k=0; k<BufferSize; k++)  SPI1_Buffer_Rx[k]=0;
00014a  f8868002          STRB     r8,[r6,#2]
                  |L5.334|
00014e  78b0              LDRB     r0,[r6,#2]  ; k
000150  1c41              ADDS     r1,r0,#1
000152  b2c9              UXTB     r1,r1
000154  f8058000          STRB     r8,[r5,r0]
000158  70b1              STRB     r1,[r6,#2]
00015a  2920              CMP      r1,#0x20
00015c  d3f7              BCC      |L5.334|
00015e  e02d              B        |L5.444|
                  |L5.352|
;;;128    
;;;129      /* Transfer procedure */
;;;130      while(Tx_Idx<BufferSize)
;;;131      { 
;;;132        /* Wait for SPI2 Tx buffer empty */
;;;133        while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE)==RESET);
000160  2102              MOVS     r1,#2
000162  4638              MOV      r0,r7
000164  f7fffffe          BL       SPI_I2S_GetFlagStatus
000168  2800              CMP      r0,#0
00016a  d0f9              BEQ      |L5.352|
;;;134        /* Send SPI1 data */
;;;135        SPI_I2S_SendData(SPI1, SPI1_Buffer_Tx[Tx_Idx]); 
00016c  7831              LDRB     r1,[r6,#0]  ; Tx_Idx
00016e  f8df8090          LDR      r8,|L5.512|
000172  f81a1001          LDRB     r1,[r10,r1]
000176  4640              MOV      r0,r8
000178  f7fffffe          BL       SPI_I2S_SendData
;;;136        /* Send SPI2 data */
;;;137        SPI_I2S_SendData(SPI2, SPI2_Buffer_Tx[Tx_Idx++]);
00017c  7830              LDRB     r0,[r6,#0]  ; Tx_Idx
00017e  f8191000          LDRB     r1,[r9,r0]
000182  1c40              ADDS     r0,r0,#1
000184  7030              STRB     r0,[r6,#0]
000186  4638              MOV      r0,r7
000188  f7fffffe          BL       SPI_I2S_SendData
                  |L5.396|
;;;138        /* Wait for SPI1 data reception */
;;;139        while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE)==RESET);
00018c  2101              MOVS     r1,#1
00018e  4640              MOV      r0,r8
000190  f7fffffe          BL       SPI_I2S_GetFlagStatus
000194  2800              CMP      r0,#0
000196  d0f9              BEQ      |L5.396|
;;;140        /* Read SPI1 received data */
;;;141        SPI1_Buffer_Rx[Rx_Idx] = SPI_I2S_ReceiveData(SPI1); 
000198  4640              MOV      r0,r8
00019a  f7fffffe          BL       SPI_I2S_ReceiveData
00019e  7871              LDRB     r1,[r6,#1]  ; Rx_Idx
0001a0  5468              STRB     r0,[r5,r1]
                  |L5.418|
;;;142        /* Wait for SPI2 data reception */
;;;143        while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE)==RESET);
0001a2  2101              MOVS     r1,#1
0001a4  4638              MOV      r0,r7
0001a6  f7fffffe          BL       SPI_I2S_GetFlagStatus
0001aa  2800              CMP      r0,#0
0001ac  d0f9              BEQ      |L5.418|
;;;144        /* Read SPI2 received data */
;;;145        SPI2_Buffer_Rx[Rx_Idx++] = SPI_I2S_ReceiveData(SPI2); 
0001ae  4638              MOV      r0,r7
0001b0  f7fffffe          BL       SPI_I2S_ReceiveData
0001b4  7871              LDRB     r1,[r6,#1]  ; Rx_Idx
0001b6  5460              STRB     r0,[r4,r1]
0001b8  1c49              ADDS     r1,r1,#1
0001ba  7071              STRB     r1,[r6,#1]
                  |L5.444|
0001bc  7830              LDRB     r0,[r6,#0]            ;130  ; Tx_Idx
0001be  2820              CMP      r0,#0x20              ;130
0001c0  d3ce              BCC      |L5.352|
;;;146      }
;;;147    
;;;148      /* Check the corectness of written dada */
;;;149      TransferStatus3 = Buffercmp(SPI2_Buffer_Rx, SPI1_Buffer_Tx, BufferSize);
0001c2  4911              LDR      r1,|L5.520|
0001c4  480d              LDR      r0,|L5.508|
0001c6  2220              MOVS     r2,#0x20
0001c8  3920              SUBS     r1,r1,#0x20
0001ca  3032              ADDS     r0,r0,#0x32
0001cc  f7fffffe          BL       Buffercmp
0001d0  7170              STRB     r0,[r6,#5]
;;;150      TransferStatus4 = Buffercmp(SPI1_Buffer_Rx, SPI2_Buffer_Tx, BufferSize);
0001d2  480a              LDR      r0,|L5.508|
0001d4  2220              MOVS     r2,#0x20
0001d6  490c              LDR      r1,|L5.520|
0001d8  3012              ADDS     r0,r0,#0x12
0001da  f7fffffe          BL       Buffercmp
0001de  71b0              STRB     r0,[r6,#6]
;;;151      GPIO_WriteBit(GPIOC, GPIO_Pin_8, TransferStatus3);
0001e0  4c0a              LDR      r4,|L5.524|
0001e2  7972              LDRB     r2,[r6,#5]  ; TransferStatus3
0001e4  f44f7180          MOV      r1,#0x100
0001e8  4620              MOV      r0,r4
0001ea  f7fffffe          BL       GPIO_WriteBit
;;;152      GPIO_WriteBit(GPIOC, GPIO_Pin_9, TransferStatus4);
0001ee  79b2              LDRB     r2,[r6,#6]  ; TransferStatus4
0001f0  1561              ASRS     r1,r4,#21
0001f2  4620              MOV      r0,r4
0001f4  f7fffffe          BL       GPIO_WriteBit
                  |L5.504|
;;;153      /* TransferStatus3, TransferStatus4 = PASSED, if the transmitted and received data
;;;154         are equal */
;;;155      /* TransferStatus3, TransferStatus4 = FAILED, if the transmitted and received data 
;;;156         are different */
;;;157    
;;;158      while(1) 
0001f8  e7fe              B        |L5.504|
;;;159      {
;;;160      }
;;;161    }
;;;162    
                          ENDP

0001fa  0000              DCW      0x0000
                  |L5.508|
                          DCD      ||.bss||
                  |L5.512|
                          DCD      0x40013000
                  |L5.516|
                          DCD      0x40003800
                  |L5.520|
                          DCD      ||.data||+0x28
                  |L5.524|
                          DCD      0x40011000

                          AREA ||.bss||, DATA, NOINIT, ALIGN=1

                  SPI_InitStructure
                          %        18
                  SPI1_Buffer_Rx
                          %        32
                  SPI2_Buffer_Rx
                          %        32

                          AREA ||.data||, DATA, ALIGN=0

                  Tx_Idx
000000  00                DCB      0x00
                  Rx_Idx
000001  00                DCB      0x00
                  k
000002  00                DCB      0x00
                  TransferStatus1
000003  00                DCB      0x00
                  TransferStatus2
000004  00                DCB      0x00
                  TransferStatus3
000005  00                DCB      0x00
                  TransferStatus4
000006  00                DCB      0x00
                  HSEStartUpStatus
000007  00                DCB      0x00
                  SPI1_Buffer_Tx
000008  01020304          DCB      0x01,0x02,0x03,0x04
00000c  05060708          DCB      0x05,0x06,0x07,0x08
000010  090a0b0c          DCB      0x09,0x0a,0x0b,0x0c
000014  0d0e0f10          DCB      0x0d,0x0e,0x0f,0x10
000018  11121314          DCB      0x11,0x12,0x13,0x14
00001c  15161718          DCB      0x15,0x16,0x17,0x18
000020  191a1b1c          DCB      0x19,0x1a,0x1b,0x1c
000024  1d1e1f20          DCB      0x1d,0x1e,0x1f,0x20
                  SPI2_Buffer_Tx
000028  51525354          DCB      0x51,0x52,0x53,0x54
00002c  55565758          DCB      0x55,0x56,0x57,0x58
000030  595a5b5c          DCB      0x59,0x5a,0x5b,0x5c
000034  5d5e5f60          DCB      0x5d,0x5e,0x5f,0x60
000038  61626364          DCB      0x61,0x62,0x63,0x64
00003c  65666768          DCB      0x65,0x66,0x67,0x68
000040  696a6b6c          DCB      0x69,0x6a,0x6b,0x6c
000044  6d6e6f70          DCB      0x6d,0x6e,0x6f,0x70

                  __ARM_use_no_argv EQU 0
